1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, more particularly, to a semiconductor delay circuit device having a plurality of inverter circuits which are cascade-connected.
2. Description of the Related Art
A semiconductor delay circuit device is used for an optical disc system, for example, a laser disc system or a compact disc system. The semiconductor delay circuit device is used for delaying a detected signal of the optical disc system to maintain synchronization even if the center position of the optical disc is shifted. Namely, since the center position of an optical disc cannot be formed perfectly at the exact center of the disc in a production step, a semiconductor delay circuit device should be provided in the optical disc system for synchronization. Note, the semiconductor delay circuit device is, for example constituted by a plurality of inverter circuits which are cascade-connected, and an input signal of the semiconductor delay circuit device is delayed in accordance with a value of a power supply voltage applied to the plurality of inverter circuits in the semiconductor delay circuit device.
Recently, the layout pattern of prior semiconductor delay circuit devices tends to be increasingly miniaturized by a requirement of large scale integration, and thus, inverter circuits are arranged adjacent to one another. The same conduction type (P-channel type or N-channel type) transistors of the plurality of inverter circuits in the semiconductor delay circuit device are then arranged such that their source regions are integrally formed with each other to constitute a common source region. In this case, a substrate contact diffusion region, which is an N.sup.+ layer or P.sup.+ layer that is an opposite conduction type relative to the common source region and has a higher impurity density than a substrate, is arranged for the common source region separately from the common source region. The common source region and substrate contact diffusion region are connected to power sources through aluminum wirings.
However, when a specific transistor is operating with the above arrangement, an operation current of the transistor flows to an aluminum wiring through the common source region, that is, the operation current of the transistor does not flow only through a source region, which is the common source region, of the specific transistor, but also flows through a source region, which is also the common source region, of a transistor neighboring the specific transistor. Then, due to contact resistance between the common source region and the aluminum wiring, etc., source potentials of the specific and neighboring transistors which have the common source region may be influenced by each other.
Further, in the layout pattern of the prior semiconductor delay circuit device, lines that connect the respective source and drain regions of the P-channel type and N-channel type transistors run in parallel with each other, and a polysilicon layer constituting a gate electrode and an aluminum wiring for connecting the drain region of the respective transistor are constituted by combining linear portions. Therefore, a pattern forming a single inverter circuit may have many useless portions marking the overall pattern larger. Additionally, in the layout pattern of the prior semiconductor delay circuit device, as the number of turning rows increases, the duty ratio of an output waveform gradually changes from the duty ratio of a first input waveform. These problems in the prior semiconductor delay circuit device will be described latest in detail with reference to the accompanying drawings.